"Another aspect of our work involves split lot analysis whereby some of a lot purposely receive non-standard processing – experiments carried out in a bid to qualify the introduction of a modified process step with a view to improving yield trends." - Emily Gleeson, Low Yield Analyst
My work as a Low Yield Analysis Engineer is based at the Intel FAB 24 site in Leixlip, Co. Kildare. The company is the leading semiconductor manufacturer and produces microprocessors and chip sets used in desktops, laptops, servers, home entertainment systems, mobile phones, digital cameras and mp3 players. Microprocessors, referred to as ‘die’, are manufactured on circular silicon wafers and are transported to each manufacturing step in groups of 25, known as a ‘lot’.
The Low Yield Analysis group (LYA) is one of six sub-groups within the Yield Department. LYA engineers and technicians operate as ’forensic’ scientists in the plant, investigating why and how the yield on any ‘lot’ is below target.
My day starts at 8am with ergonomic stretching exercises with others from the Yield department in Intel. At 8.15am The LYA engineers meet the Failure Analysis (FA) technicians for task up-dates.
All wafers undergo a series of electrical tests and are categorised according to their failure mode.
My job involves analysing the pass/fail trends in this data (called sort data) along with other parameters and statistics to ascertain if and why something went wrong in the manufacturing process flow. The job also involves examining lots that are held at end-of-line, due to any variation in standard processing. Such lots cannot be released until reviewed by LYA.
Another aspect of our work involves split lot analysis whereby some of a lot purposely receive non-standard processing – experiments carried out in a bid to qualify the introduction of a modified process step with a view to improving yield trends.
11am – our group meet for a daily huddle (or cuddle as it is often referred to!). During this time we categorise all lots that have reached end-of-line and delegate work appropriately.
12 noon – lunch time: today we have a lunch time party to celebrate a key milestone on Intel’s new factory FAB 24-2 road map – we have a mini-Olympic games. The music is blaring, popcorn and candy floss are flowing.
1pm – The yield department meeting with all Group Leaders present. I am presenting on behalf of LYA today and am sort of nervous as I am still relatively new to this job.
The yield model needs to be run before the meeting – hope it matches or runs close to the actual yield. If not there will be some explaining to be done. The meeting goes according to plan. I also have to make this presentation at our ‘virtual factory’ meeting (phone conference) this evening with our colleagues in Portland, Oregon and New Mexico.
There are thousands of instructor-taught and web-based training courses at Intel. I schedule myself for at least one course a week – this week I will complete a course on effective meetings.
In addition to my engineering chores I also take part in a number of community projects such as teaching internet skills to students with learning disabilities, and involvement in promoting science and technology in schools.
5pm sees the end of the working day…. time for a 10 km run to recharge my batteries.
Emily Gleeson ~ www.iopireland.org